Multi-emitter bipolar transistor for bandgap reference circuits

ABSTRACT

A transistor includes a substrate region ( 14 ) of a first type (P) of conductivity in a semiconductor material layer of the same type (P) of conductivity, at least a first contact region ( 13 ) of the first type (P+) of conductivity inside the substrate region ( 14 ) and adjacent to a first terminal (C) of the transistor, a well ( 11 ) of second type (N) of conductivity placed inside the substrate region ( 14 ), wherein the well ( 11 ) of second type (N) of conductivity includes at least a second contact region ( 12 ) of a second type of conductivity (N+) adjacent to a region of a second terminal (B) of the transistor, and a plurality of third contact regions ( 10 ) of the first type of conductivity (P+) adjacent to a plurality of regions of a third terminal (E 1,  . . . , E 3 ) of the transistor interposed each one ( 10 ) and other ( 12 ) by proper insulating shapes ( 20 ).

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application is based upon and claims priority from prior European Patent Application No. 00830851.2, filed on Dec. 28, 2000, the entire disclosure of which is herein incorporated by reference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The invention generally relates to a multi-emitter bipolar transistor for bandgap reference circuits, and more particularly to a multi-emitter vertical bipolar transistor to be used as reference in bandgap circuits.

[0004] 2. Description of the Related Art

[0005] In the modern microelectronic devices based on CMOS technology voltages are internally produced and used, such as, for example, negative voltages and/or high voltages, distinct from supply voltage.

[0006] The circuits for the management of the various produced voltages need of a precise and stable voltage reference both at the supply voltage oscillations and at the temperature changes. A reference of such a nature is obtained by means of a circuit known as “bandgap reference”.

[0007] Such a circuit usually uses bipolar transistors so as to make full use of the characteristic of the bipolar transistors to have a current voltage law exponentially linked, in turn correlated with the energetic gap of the starting semiconductor.

[0008] In fact the way of working of the bandgap circuits provides for comparing the current flowing in a bipolar with that flowing in other “n” bipolars connected in parallel. Each one of “n+1” bipolars is connected as diode, that is it has the base and collector electrodes short circuited.

[0009] In the reference bandgap circuits, implemented by CMOS technology with p type substrate, or implemented in technologies according to which masks or specific steps are not provided to realize bipolar transistors, pnp type vertical transistors are used.

[0010] For a n type substrate the dual principle is valid.

[0011] The pnp transistor is implemented making opportunely full use of some steps and necessary structures for the realization of complementary MOSFET transistors, that is the availability of an usual P+ implant, adapted for making the source and drain junction of the MOSFET transistors, and of a N well, adapted for making the channel of the MOS transistor with p channel and the p substrate itself, makes easily available the possibility to obtain the pnp vertical bipolar transistor.

[0012] In the process of implementation of these pnp type vertical bipolar transistors all the projecting laws relating to the distances and minimum sizes, relating to the active areas in the N well and to the P+ active areas placed in the substrate around the N well should be respected.

[0013] By implementing a structure with this standard CMOS technology a remarkable waste of area is obtained and, therefore, there is a lower integration of the devices.

[0014] Moreover an adequate electric coupling among the devices making the circuit is not obtainable.

[0015] Accordingly, there exists a need for overcoming the disadvantages of the prior art as discussed above.

SUMMARY OF THE INVENTION

[0016] In view of the state of the art described, a multi-emitter bipolar transistor for bandgap reference circuits, according to a preferred embodiment of the present invention, is able to avoid to the problems of the prior art.

[0017] According to a preferred embodiment of the present invention, a transistor comprises a substrate region of a first type of conductivity in a semiconductor material layer of the same type of conductivity, at least a first contact region of the first type of conductivity inside the substrate region and adjacent to a first terminal of the transistor, a well of second type of conductivity placed inside the substrate region, wherein the well of second type of conductivity comprises at least a second contact region of a second type of conductivity adjacent to a region of a second terminal of the transistor, adjacent to a region of a second terminal of the transistor, and a plurality of third contact regions of the first type of conductivity adjacent to a plurality of regions of a third terminal of the transistor interposed each other by opportune insulating shapes.

[0018] Thanks to the present invention it is possible to realize a remarkable saving of silicon area.

[0019] Moreover it is possible to have a better coupling of the electric characteristics of the device.

[0020] Moreover it is possible to have a simplification of the interconnections among the several devices of the circuit.

[0021] Moreover it is possible to have an optical shield of the multi-emitter bipolar devices constituting the bandgap reference circuit.

[0022] In particular, this last advantage allows a better stability of the voltage reference in devices with an Ultra Violet (UV) erasing package and, in general, for the steps of Electrical Wafer Sort (EWS), that is for the testing steps on wafer of every single chip even if it is not make in the dark.

BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The features and the advantages of the present invention will be made evident by the following detailed description of embodiments thereof which are illustrated as non-limiting examples in the annexed drawings, wherein:

[0024]FIG. 1 shows a reference bandgap circuit according to the prior art;

[0025]FIG. 2 shows in particular a device of FIG. 1;

[0026]FIG. 3 shows a top plan view of a pnp bipolar transistor according to the prior art;

[0027]FIG. 4 shows the device of FIG. 3 along the section line IV-IV;

[0028]FIG. 5 shows an embodiment of a matrix structure of the reference circuit according to the prior art;

[0029]FIG. 6 shows a top plan view of a pnp bipolar transistor according to a preferred embodiment of the present invention;

[0030]FIG. 7 shows the device of FIG. 6 along the section line VI-VI; and

[0031]FIG. 8 shows an embodiment of a matrix structure of the reference circuit according to a preferred embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0032] In FIG. 1 a reference bandgap circuit according to the prior art is shown, wherein a reference supply line Vbgap and a couple of pnp bipolar transistor Q1 and Q2 that are connected as diode, that is having the respective base Q1 b and Q2 b and collector Q1 c and Q2 c electrodes short circuited, are noted.

[0033] The way of working provides for comparing, by means of a differential amplifier 1, connected at a side to a supply voltage Vcc and at the other side to ground, the voltage drops Vbe1 and Vb2 caused by the currents I1 and I2 that flow on the respective emitter branches of the transistors Q1 and Q2.

[0034] Moreover such a circuit must cause the currents I1 and I2 to be constant by means of a feedback system.

[0035] The currents that flow in the two branches must be one the exact multiple of the other, particularly I2=n*I1.

[0036] To obtain this, it is well known to a skilled person to realize a bipolar transistor Q2 repeating “n” times the bipolar transistor Q1, as shown in FIG. 1.

[0037] In fact Q2 is made as a copy of “n” transistors Q1, all transistors being connected in parallel, as shown in FIG. 2.

[0038] Moreover, as it is well known, the vertical bipolar transistors Q1 and Q2 are made on a silicon wafer making proper full use of some steps, masks and necessary structures for the implementing of complementary MOSFETs, that is CMOS (not shown in Figure), inside the bandgap reference circuit.

[0039] In FIG. 3 a top plan view of a pnp bipolar transistor according to the prior art is shown.

[0040] In a technological process of CMOS type, the availability of a P+ type typical implant 2, for the realization of the source and drain junctions of the MOSFET transistors, and of N type well 3, wherein the conductive channel of the p type MOSFET transistors is made and of a substrate 4 of the CMOS device, allows to realize a pnp type vertical bipolar transistor, without any dedicated process steps.

[0041] In fact the P+ type implant 2 represents the emitter and the collector electrode of the pnp vertical transistor, while the N type well 3 represents the base electrode of the pnp vertical transistor.

[0042] In FIG. 4 a view of the device of FIG. 3 along the section line IV-IV is shown and the sections of the N+ type implant ring 5 in the base region and the P+ type implants 6 and 7 in the collector and emitter region of the vertical bipolar transistor, adapted to contact respectively the base, the collector and the emitter, are noted.

[0043] The P+ type diffusion 7 of the emitter can be projected in function of the particular needs which the transistor has to respect according the known technology.

[0044] The building of a pnp vertical transistor must take into account the geometrical size of the bipolar transistor itself, because this behaves as vertical bipolar transistor only when the distance between the emitter and collector electrodes in the longitudinal direction is bigger than the thickness of the base region, otherwise the resulting bipolar transistor behaves as lateral bipolar transistor.

[0045] When a bandgap circuit on a layout is realized, in order to have a good reproducibility of the currents, a matrix structure 8 is realized, as shown in FIG. 5.

[0046] Such a matrix structure 8 represents, in the specific embodiment, a matrix having five columns by five rows, in the cross-points of which there are some transistors placed but not used.

[0047] At every cross-point of the structure 8 there is, therefore, the representation of a pnp type bipolar transistor Q1, repeated n times. In fact in the center of every cross there is the emitter terminal 31, and moving through the board of the device, the base terminal 32 and the collector terminal 33 is found.

[0048] The other transistors are placed around it and eventually some other transistors are not connected and not used. This is to obviate the defects of symmetry of the structure and to reproduce the currents as similarly as possible.

[0049] In FIG. 6 a top plan view of a pnp bipolar transistor made by a CMOS technology according to the present invention is shown.

[0050] As shown in such a Figure, the inventive solution provides for only one N type well 11, adapted to contain the “n+1” P+ type implants 10.

[0051] The N type well 11 represents the base electrode, while the “n+1” implants represent the pnp bipolar emitters.

[0052] In FIG. 7 the device of FIG. 6 along the section line VI-VI is shown, wherein a P type substrate 14, making the collector, that results connectable by means of a P+ type ring 13 that rounds all the inventive structure, and the N type well 11, making the base, connected by means of N+ type ring 12, are noted. The N type well 11 contains the “n+1” emitters 10, made by the P+ type implants.

[0053] What is represented in such a Figure, therefore, it is a pnp type bipolar transistor, having the P type substrate 14 with a P+ type contact region 13 adjacent to its collector terminal C, and the N type well 11 with N+type contact regions 12 adjacent to its base terminal B and with P+ type contact regions adjacent to their emitter terminals E1, . . . , E3.

[0054] Suitable structures 20, such as oxides or junction wells, to isolate the emitters E1, . . . , E3 with respect to each other and the well 12 are provided.

[0055] It is to be noted that this structure is possible because the traditional bandgap circuit provides that the base and collector short circuited to the ground.

[0056] In FIG. 8 an embodiment of a matrix structure of the reference circuit according to the present invention is shown.

[0057] In such a Figure a matrix 15 that results to have five columns 18, . . . , 22 and five rows 23, . . . , 27.

[0058] At every cross an emitter electrode is placed that is interconnected or floating with respect to the other emitter electrodes.

[0059] From the specific embodiment shown in FIG. 8, a matrix 15 results having an interconnection scheme such as that described in the successive table: 18 19 20 21 22 23 x e x e x 24 e e x e e 25 e x E x e 26 e e x e e 27 x e x e x

[0060] where “x” indicates a floating emitter, “e” an emitter interconnected with the other emitters and “E” an emitter of the single side.

[0061] The matrix 15 results to be perfectly symmetrical and with better matching characteristics, that is the transistors are much more similar to each other, with respect to the traditional embodiments. This because a structure 16 is repeated more times and it is so as to have structures 17 equal to the structure 16 and connected to each other with the lower number of interconnections.

[0062] In this way the transistor that must be used alone, that is in the single branch of the reference bandgap circuit and is indicated with the symbol “E” in the previous table, is arranged in the center of the matrix 15, so that the matrix 15 itself is realized with the highest number of implementable transistors, so as to increase the system symmetry and therefore the reproducibility of the transistors.

[0063] Making the matrix 15 with “n+1” emitters near each other, the matching is enhanced both for the smaller occupied area and because it is not necessary to short circuit every base and collector electrode with metal lines.

[0064] Inserting the “n+1” emitters in the base 11, multiple advantages are obtained such as, for example: a) saving of silicon area, because by inserting the “n+1” emitters in a N type unique well 11 the only law to be respected is the minimum distance between the active areas of the emitters 10; b) it is not necessary to short circuit the bases and the collectors each other with metal lines, but with the present invention it is sufficient to short circuit only the unique large base and the collector; c) not short circuiting the bases and the collectors allows to contact the n emitters with each other and the central emitter with an operational amplifier (not shown in Figure) with a structure of interconnection wherein intercrosses among the bases and collector do not exist.

[0065] This last advantage gives the possibility to let the higher interconnection level free to be, therefore, used as an optical shield against the light for the whole system of transistors adapted to generate the bandgap voltage, in the case the integrated circuit is mounted onto an UV erasing package, for example, for EPROM memories.

[0066] Moreover the possibility to have this shield allows that the EWS phase on wafer can develop with a biased circuit and not in the dark because the shield guaranties the stability of the bandgap circuit and therefore also of the bandgap voltage.

[0067] Other embodiments, according to the present invention, are depicted in the following tables: C¹ C² C³ C⁴ C⁵ R¹ e e x e x R² e e e e e R³ e e E e e R⁴ e e e e e R⁵ x e x e x

[0068] where R¹, . . . , R⁵ are the number of the rows an C¹, . . . ,C⁵ are the number of the columns and “x”, “e” and “E” indicates respectively the floating emitter, the emitter interconnected with the other emitters and the emitter of the single side; C¹ C² C³ R¹ e x x R² x E x R³ e x E

[0069] where R¹, . . . , R³ are the number of the rows and C¹, . . . , C³ are the number of the columns and, again, “x”, “e” and “E” indicates respectively the floating emitter, the emitter interconnected with the other emitters and the emitter of the single side; C¹ C² C³ R¹ x e x R² e E e R³ x e x

[0070] where R¹, . . . , R³ are the number of the rows and C¹, . . . , C³ are the number of the columns and, again, “x”, “e” and “E” indicates respectively the floating emitter, the emitter interconnected with the other emitters and the emitter of the single side; C¹ C² C³ R¹ e e e R² e E e R³ e e e

[0071] where R¹, . . . , R³ are the number of the rows and C¹, . . . , C³ are the number of the columns and, again, “e” and “E” indicates respectively the emitter interconnected with the other emitters and the emitter of the single side.

[0072] In the present embodiments pnp type vertical bipolar transistor are used, but the inventive solution also provides for bandgap reference circuits made by npn type bipolar transistors connected in diode configuration.

[0073] The present invention is destined, therefore, both to standard CMOS processes, EPROM processes, and other specific processes such as, for example, BCD and/or BiCMOS, if in the reference branches a bipolar connected as diode is used.

[0074] While there has been illustrated and described what are presently considered to be the preferred embodiments of the present invention, it will be understood by those of ordinary skill in the art that various other modifications may be made, and equivalents may be substituted, without departing from the true scope of the present invention.

[0075] Additionally, many modifications may be made to adapt a particular situation to the teachings of the present invention without departing from the central inventive concept described herein. Furthermore, an embodiment of the present invention may not include all of the features described above. Therefore, it is intended that the present invention not be limited to the particular embodiments disclosed, but that the invention include all embodiments falling within the scope of the appended claims. 

What is claimed is:
 1. A transistor comprising: a substrate region of a first type of conductivity in a semiconductor material layer of the same type of conductivity; at least a first contact region of the first type of conductivity inside the substrate region and adjacent to a first terminal of the transistor; a well of second type of conductivity placed inside the substrate region, wherein the well of second type of conductivity comprises at least a second contact region of a second type of conductivity adjacent to a region of a second terminal of the transistor; and a plurality of third contact regions of the first type of conductivity adjacent to a plurality of regions of a third terminal of the transistor interposed each one and other by proper insulating shapes.
 2. The transistor according to claim 1, wherein the substrate region has a first resistivity value, and that the first and second contact regions have a second value of resistivity lower than the first value of resistivity.
 3. The transistor according to claim 1, wherein the well of the second type of conductivity has a third value of resistivity, and that the third contact regions have a fourth value of resistivity lower than the third value of resistivity.
 4. The transistor according to claim 1, wherein the second type of conductivity is short circuited with the first contact region of the first type of conductivity.
 5. The transistor according to claim 1, wherein the first contact regions are adjacent to collector terminal regions.
 6. The transistor according to claim 1, wherein the second contact regions are adjacent to emitter regions.
 7. The transistor according to claim 1, wherein the third contact regions are adjacent to base terminal regions.
 8. The transistor according to claim 1, wherein the first type of conductivity is p type and the second type of conductivity is n type, so as to realize a pnp bipolar transistor.
 9. The transistor according to claim 1, wherein the first type of conductivity is n type and the second type of conductivity is p type, so as to realize a npn bipolar transistor.
 10. The transistor according to claim 1, wherein the first and second contact regions are made by the same implant of dopant atoms.
 11. The transistor according to claim 1, wherein the insulating regions are made by proper insulating means.
 12. A connection matrix for a multi-emitter bipolar transistor comprising: a plurality of columns and a plurality of rows an emitter electrode being provided at every crossing of the plurality of columns and of the plurality of rows, wherein the multi-emitter bipolar transistor has an emitter electrode of single side in the central crossing of the plurality of columns and of the plurality of rows, the multi-emitter bipolar transistor having a first plurality of emitter electrodes interconnected with each other and the first plurality of emitter electrodes placed in a symmetric configuration with respect to the emitter electrode of single side.
 13. The connection matrix according to claim 12, wherein the multi-emitter bipolar transistor has a second plurality of emitter electrodes placed in a symmetric configuration with respect to the emitter electrode of single side, the second plurality of emitter electrodes being floating.
 14. The connection matrix according to claim 13, wherein the first and second pluralities of emitter electrodes are alternated with each other.
 15. A transistor comprising: a substrate region of a first type of conductivity in a semiconductor material layer of the same type of conductivity; at least a first contact region of the first type of conductivity inside the substrate region and adjacent to a first terminal of the transistor; a well of second type of conductivity placed inside the substrate region, wherein the well of second type of conductivity comprises at least a second contact region of a second type of conductivity adjacent to a region of a second terminal of the transistor; and a plurality of third contact regions of the first type of conductivity adjacent to a plurality of regions of a third terminal of the transistor interposed each one and other by proper insulating shapes, wherein the well of second type of conductivity is short circuited with the substrate region of first type of conductivity.
 16. An electronic device comprising: a circuit supporting substrate; and at least one bipolar transistor disposed on the circuit supporting substrate, each of the at least one bipolar transistor comprising: a plurality of columns and a plurality of rows, an emitter electrode being provided at every crossing of the plurality of columns and of the plurality of rows, and wherein each of the at least one bipolar transistor having an emitter electrode of single side in the central crossing of the plurality of columns and of the plurality of rows, and wherein each of the at least one bipolar transistor having a first plurality of emitter electrodes placed in a symmetric configuration with respect to the emitter electrode of single side.
 17. The electronic device of claim 16, wherein the first plurality of emitter electrodes are interconnected with each other.
 18. The electronic device of claim 17, wherein each of the at least one bipolar transistor has a second plurality of emitter electrodes placed in a symmetric configuration with respect to the emitter electrode of single side, the second plurality of emitter electrodes being floating.
 19. The electronic device of claim 16, wherein each of the at least one bipolar transistor has the first plurality of emitter electrodes interconnected with each other and a second plurality of emitter electrodes placed in a symmetric configuration with respect to the emitter electrode of single side, the second plurality of emitter electrodes being floating.
 20. The electronic device of claim 16, wherein each of the at least one bipolar transistor has a second plurality of emitter electrodes placed in a symmetric configuration with respect to the emitter electrode of single side, the second plurality of emitter electrodes being floating, and wherein the first and second pluralities of emitter electrodes are alternated with each other. 